Education

  • École Polytechnique Fédéral de Lausanne (EPFL), Lausanne, Switzerland
    Doctoral Program in Computer and Communication Sciences (EDIC), since 09/2019
  • National Taiwan University (NTU), Taipei, Taiwan
    Bachelor of Science in Electrical Engineering, 09/2015 - 06/2019
  • Taipei First Girls' High School (TFG), Taipei, Taiwan. 09/2012 - 06/2015

Industry Experience

  • Internship at Cadence Design Systems, Munich, Germany
    Software Engineering Intern, 04/2023 - 09/2023

Research

Logic Synthesis (Electronic Design Automation, EDA)

  • Synthesis and Optimization for Emerging Technologies in Superconducting Electronics (since 08/2020)
    Advisor: Professor Giovanni De Micheli, EPFL
  • Scalable and Generic Logic Synthesis (since 02/2020)
    Advisor: Professor Giovanni De Micheli, EPFL
  • Threshold Logic Canonicalization and Weight-Sharing Synthesis (08/2016 - 08/2019)
    Advisor: Professor Jie-Hong Roland Jiang, EE, NTU

Computational Neuroscience

  • Adaptive Reinforcement Learning on Navigational Task with Biological Model of Cognitive Spatial Map (09/2019 - 01/2020)
    Advisor: Professor Wulfram Gerstner, EPFL
  • Modeling of The Spatial Perception System (09/2017 - 01/2018)
    Advisor: Professor Shyh-Kang Jeng, EE, NTU

Molecular Biology

  • Mitochondrial Protein CYP11A1 Changes Mitochondrial Morphology (01/2013 - 04/2015)
    Advisor: Professor Bon-Chu Chung, Academia Sinica, Taiwan

Publications

  • Siang-Yun Lee, Christopher L Ayala, Giovanni De Micheli. "Impact of Sequential Design on The Cost of Adiabatic Quantum-Flux Parametron Circuits," IEEE Transactions on Applied Superconductivity (TAS). (IEEEXplore)
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Customizable On-the-fly Design Space Exploration for Logic Optimization of Emerging Technologies," 2023 International Workshop on Logic and Synthesis (IWLS).
  • Dewmini Sudara Marakkalage, Marcel Walter, Siang-Yun Lee, Robert Wille, and Giovanni De Micheli. "Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions," 2023 International Workshop on Logic and Synthesis (IWLS). (Best student paper award nominee)
  • Siang-Yun Lee and Giovanni De Micheli. "Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (IEEEXplore)
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "External Don't Cares in Logic Synthesis," 2022 International Workshop on Boolean Problems (IWSBP).
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications," 2022 International Workshop on Logic and Synthesis (IWLS). (Best Student Paper Award) (arXiv)
  • Hanyu Wang, Siang-Yun Lee, and Giovanni De Micheli. "A Cost-generic Resubstitution Algorithm with Customizable Cost Functions," 2022 International Workshop on Logic and Synthesis (IWLS).
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits," 2022 Design Automation Conference (DAC).
  • Giulia Meuli, Vinicius Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca Amaru, Scott Chase, Jamil Kawa, and Giovanni De Micheli. "Majority-based Design Flow for AQFP Superconducting Family," 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). (IEEEXplore)
  • Heinz Riener, Siang-Yun Lee, Alan Mishchenko, and Giovanni De Micheli. "Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis," 2022 Asia and South Pacific Design Automation Conference (ASP-DAC). (IEEEXplore)
  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, and Giovanni De Micheli. "A Simulation-Guided Paradigm for Logic Synthesis and Verification," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (IEEEXplore)
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits," 2021 International Workshop on Logic and Synthesis (IWLS). (arXiv)
  • Heinz Riener, Siang-Yun Lee, Alan Mishchenko, and Giovanni De Micheli. "Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis," 2021 International Workshop on Logic and Synthesis (IWLS).
  • Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition," 2021 International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). (IEEEXplore)
  • Eleonora Testa, Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits," 2021 Asia and South Pacific Design Automation Conference (ASP-DAC). (IEEEXplore)
  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, and Giovanni De Micheli. "Simulation-Guided Boolean Resubstitution," 2020 International Workshop on Logic and Synthesis (IWLS). (arXiv)
  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks,” 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). (IEEEXplore)
  • Siang-Yun Lee, Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton. "Enumeration of Minimum Fanout-Free Circuit Structures," 2019 International Workshop on Logic and Synthesis (IWLS). (PDF)
  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Canonicalization of Threshold Logic Representation and Its Applications,” 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). (IEEEXplore)

Awards

  • Best Student Paper Award, International Workshop on Logic and Synthesis (IWLS), 07/2022.
    -- For the paper "An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications"
  • First Prize Award, IWLS Programming Contest, 07/2022.
  • First Prize Award, ACM/SIGDA CADathlon Programming Contest (ICCAD, Westminster CO, USA), 11/2019.
  • First Prize Award, Integrated Circuits Computer Aided Design Contest (Ministry of Education, Taiwan), 11/2017.
    -- For the project "Input Sequence Generator for System Verilog Assertion Checking".
  • Fourth Award in cellular and molecular biology, Intel International Science and Engineering Fair (ISEF, Pittsburgh PA, USA), 05/2015.
    -- For the project "Mitochondrial Protein CYP11A1 Changes Mitochondrial Morphology".

Fellowships & Grants

  • EPFL EDIC Fellowship (2019)
  • A. Richard Newton Young Student Fellow Program, 2018 Design Automation Conference (DAC)
  • Undergraduate Student Research Program, Ministry of Science and Technology, Taiwan
  • Undergraduate Scholarship, Taiwan Semiconductor Manufacturing Company (TSMC) - National Taiwan University Joint Research Center

Teaching

Lecturing at EPFL

  • CS-724 Advanced Logic Synthesis and Quantum Computing (Spring 2022, Spring 2023; co-teach with Dr. Mathias Soeken)

TA at EPFL

  • CS-472 Design Technologies for Integrated Systems (Fall 2020, Fall 2021, Fall 2022)
  • CS-173 Digital System Design (Spring 2020, Spring 2021, Spring 2022)

TA at NTU

  • Cornerstone EECS Design and Implementation (Spring 2018, Spring 2019)
  • Switching Circuit and Logic Design (Fall 2016)

Others

  • Course desinger and instructor for educational organization TimeMap: hands-on classes introducing Electrical Engineering to high school students