Siang-Yun Lee is a Ph.D. student at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli.

She graduated from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis.

Her research interests include logic synthesis, design automation for emerging technologies, and computational neuroscience. She is currently a maintainer of the EPFL logic synthesis library mockturtle.