Education

  • École Polytechnique Fédéral de Lausanne (EPFL), Lausanne, Switzerland
    Doctoral Program in Computer and Communication Sciences (EDIC), since 09/2019
  • National Taiwan University (NTU), Taipei, Taiwan
    Bachelor of Science in Electrical Engineering, 09/2015 - 06/2019
  • Taipei First Girls' High School (TFG), Taipei, Taiwan. 09/2012 - 06/2015

Research

Logic Synthesis (Electronic Design Automation, EDA)

  • Synthesis and Optimization for Emerging Technologies in Superconducting Electronics (since 08/2020)
    Advisor: Professor Giovanni De Micheli, EPFL
  • Simulation-Guided Boolean Resubstitution (02/2020 - 07/2020)
    Advisor: Professor Giovanni De Micheli, EPFL
  • Threshold Logic Canonicalization and Weight-Sharing Synthesis (08/2016 - 08/2019)
    Advisor: Professor Jie-Hong Roland Jiang, EE, NTU

Computational Neuroscience

  • Adaptive Reinforcement Learning on Navigational Task with Biological Model of Cognitive Spatial Map (09/2019 - 01/2020)
    Advisor: Professor Wulfram Gerstner, EPFL
  • Modeling of The Spatial Perception System (09/2017 - 01/2018)
    Advisor: Professor Shyh-Kang Jeng, EE, NTU

Molecular Biology

  • Mitochondrial Protein CYP11A1 Changes Mitochondrial Morphology (01/2013 - 04/2015)
    Advisor: Professor Bon-Chu Chung, Academia Sinica, Taiwan

Publications

  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, and Giovanni De Micheli. "Simulation-Guided Boolean Resubstitution," 2020 International Workshop on Logic and Synthesis (IWLS) (ArXiv)
  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks,” 2019 IEEE/ACM International Conference On Computer-Aided Design (ICCAD). (IEEEXplore)
  • Siang-Yun Lee, Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton. "Enumeration of Minimum Fanout-Free Circuit Structures," 2019 International Workshop on Logic and Synthesis (IWLS) (PDF)
  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Canonicalization of Threshold Logic Representation and Its Applications,” 2018 IEEE/ACM International Conference On Computer-Aided Design (ICCAD). (IEEEXplore)

Awards

  • First Prize Award, ACM/SIGDA CADathlon Programming Contest (ICCAD, Westminster CO, USA), 11/2019.
  • First Prize Award, Integrated Circuits Computer Aided Design Contest (Ministry of Education, Taiwan), 11/2017.
    -- For the project “Input Sequence Generator for System Verilog Assertion Checking”.
  • Fourth Award in cellular and molecular biology, Intel International Science and Engineering Fair (ISEF, Pittsburgh PA, USA), 05/2015.
    -- For the project "Mitochondrial Protein CYP11A1 Changes Mitochondrial Morphology".

Fellowships & Grants

  • EPFL EDIC Fellowship (2019)
  • A. Richard Newton Young Student Fellow Program, 2018 Design Automation Conference (DAC)
  • Undergraduate Student Research Program, Ministry of Science and Technology, Taiwan
  • Undergraduate Scholarship, Taiwan Semiconductor Manufacturing Company (TSMC) - National Taiwan University Joint Research Center

Teaching

TA at EPFL

  • CS-472 Design Technologies for Integrated Systems (Fall 2020)
  • CS-173 Digital System Design (Spring 2020)

TA at NTU

  • Cornerstone EECS Design and Implementation (Spring 2018, Spring 2019)
  • Switching Circuit and Logic Design (Fall 2016)

Others

  • Course desinger and instructor for educational organization TimeMap: hands-on classes introducing Electrical Engineering to high school students