Projects

Logic Synthesis

Synthesis and Optimization for Emerging Technologies in Superconducting Electronics

(since 08/2020)
Advisor: Professor Giovanni De Micheli, EPFL

Simulation-Guided Boolean Resubstitution

(02/2020 - 07/2020)
Advisor: Professor Giovanni De Micheli, EPFL

  • Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, and Giovanni De Micheli. "Simulation-Guided Boolean Resubstitution," 2020 International Workshop on Logic and Synthesis (IWLS) (ArXiv)

Threshold Logic Canonicalization and Weight-Sharing Synthesis

(08/2016 - 08/2019)
Advisor: Professor Jie-Hong Roland Jiang, EE, NTU

  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks,” 2019 IEEE/ACM International Conference On Computer-Aided Design (ICCAD). (IEEEXplore)
  • Siang-Yun Lee, Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton. "Enumeration of Minimum Fanout-Free Circuit Structures," 2019 International Workshop on Logic and Synthesis (IWLS) (PDF)
  • Siang-Yun Lee, Nian-Ze Lee, and Jie-Hong R. Jiang. “Canonicalization of Threshold Logic Representation and Its Applications,” 2018 IEEE/ACM International Conference On Computer-Aided Design (ICCAD). (IEEEXplore)