Synthesis and Optimization for Emerging Technologies in Superconducting Electronics

(since 08/2020, PhD research)
Advisor: Professor Giovanni De Micheli, EPFL

The growing demand for computationally-heavy applications nowadays draws increasing attention to superconducting electronics (SCE) because of its capability of high-speed computation and low energy consumption. In parallel to the rapid development of SCE technologies such as the rapid single-flux quantum (RSFQ) and the adiabatic quantum-flux parametron (AQFP), there is a need to adapt the existing electronic design automation (EDA) algorithms to address the design constraints arising from these emerging technologies.

In particular, two special constraints are imposed by both RSFQ and AQFP circuits:

  1. Path balancing: Logic gates in both AQFP and RSFQ are clocked, and the input signals of a logic gate must arrive at the same time. In other words, all data paths must be of the same length. Whereas shortening longer paths is not always possible, buffers need to be inserted to delay shorter paths.
  2. Fanout branching: As the output current of an AQFP gate, or the output pulse of an RSFQ gate, is limited, it has to be amplified by a splitter before branching into multiple fanouts. In AQFP, splitters are clocked (i.e., participate in path balancing); in RSFQ, splitters are not clocked.

In this project, we adapt existing logic synthesis algorithms, or design new algorithms, to deal with these special constraints during logic optimization. In [1], an optimization flow for AQFP is designed to minimize the cost for both logic gates and buffers/splitters, where the increase of fanout is limited and depth optimization is prioritized. In [2,4], the problem of AQFP buffer/splitter insertion is further investigated. Due to the interplay between path balancing and fanout branching in AQFP, a globally optimal buffer insertion scheme cannot be found easily. We proposed a linear-time irredundant buffer insertion algorithm and a scheduling-based technique to further optimize it heuristically. The impact of different technology assumptions are also studied.

Related publications

  1. Eleonora Testa, Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits," 2021 Asia and South Pacific Design Automation Conference (ASP-DAC). (IEEEXplore)
  2. Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits," 2021 International Workshop on Logic and Synthesis (IWLS). (arXiv, video)
  3. Giulia Meuli, Vinicius Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca Amaru, Scott Chase, Jamil Kawa, and Giovanni De Micheli. "Majority-based Design Flow for AQFP Superconducting Family," 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). (IEEEXplore)
  4. Siang-Yun Lee, Heinz Riener, and Giovanni De Micheli. "Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits," 2022 Design Automation Conference (DAC). (video)
  5. Siang-Yun Lee, Christopher L Ayala, Giovanni De Micheli. "Impact of Sequential Design on The Cost of Adiabatic Quantum-Flux Parametron Circuits," IEEE Transactions on Applied Superconductivity (TAS). (IEEEXplore)

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