Siang-Yun (also known as Sonia) Lee is a R&D engineer at Cadence Design Systems working in Munich, Germany. She did her Ph.D. at the Integrated Systems Laboratory at EPFL, Switzerland led by Prof. Giovanni De Micheli from 2019 to 2024. Her thesis was about contemporary logic synthesis techniques with an application to emerging technologies.

Before that, she obtained her bachelor’s degree from the Department of Electrical Engineering of National Taiwan University in 2019, where she worked with Prof. Jie-Hong Roland Jiang on threshold logic synthesis.

Her research interests include logic synthesis, design automation for emerging technologies, and computational neuroscience. She is also a maintainer of the EPFL logic synthesis library mockturtle.